Abstract: Timing analysis and closure of CDC signals in asynchronous clock domains is an important guarantee to the function correctness of high frequency large scale digital circuits. In order to reduce the design area, a sliding window timing analysis method of CDC signals is proposed, which can execute timing analysis and closure by setting appropriate timing constraint window for each CDC path under each corner. This method can avoid the increase of cell area caused by fake timing violations and unnecessary timing fixing under over-constraint, which often happened in the fixed constraint method. The proposed method can also reduce the backend workload of CDC circuits. The experiment under 16 nm process shows that the proposed method can significantly save the design area compared with the fixed constraint method.

Key words: clock domain, CDC, sliding window, timing analysis, fixed constraint