Abstract:  In recent years, traditional computer architectures have gradually been faced with severe bottlenecks of “Memory Wall” and “Power Wall”, with the step-down Moores law. However, many other new forms of computing paradigms and computer architectures have been proposed, including neuromorphic computing. Given the characteristic of computing in memory, neuromorphic computing plays a vital role in breaking down the limitation caused by both “Memory Wall” and “Power Wall” constraints in Von Neumann architecture. Many neuromorphic applications on neuromorphic processors have already been demonstrated as high efficiency and accuracy. Currently, in the application scenarios of large-scale biological neural networks, it is necessary to improve the scalability of multi-core neuromorphic processors and maintain their high data throughput and low transmission delay. Today, most multi-core neuromorphic processors adopt a network-on-chip (NoC) as the interconnect structure. However, there are still relatively few verification studies on such NoC. Given the importance of NoC in designing a neuromorphic processors, it is quite necessary to set up a complete and robust NoC functional verification platform for neuromorphic processors. The purpose of this paper is to generate the stimulus files required for behavioral and FPGA hardware-level testing based on the randomization method, and to achieve a more comprehensive functional verification through efficient processing of log files.

Key words: network on chip, field programmable gate array(FPGA), functional verification, spiking neural network(SNN), neuromorphic computing