Abstract: Spiking neural networks (SNN) can be deployed on neuromorphic processors to complete various tasks. Network on Chip (NoC) can solve the complex interconnection and communication problems with less resources and power consumption. NoC is widely adopted in neuromorphic processors to support communication between neurons. The instantaneous burst communication patten of SNN gene- rates a large number of spikes at each time step. At this time, NoC reaches its saturation rapidly, causing network congestion. Meanwhile, non-congestion-aware routing algorithms further aggravates the congestion state of NoC. How to effectively process these spikes at each timestep, reduce the delay of the network, and increase the throughput has become the problem we need to solve at present. The paper first analyzes the instantaneous burst communication characteristics of SNN. Then, a congestion- aware Hamilton path routing algorithm with the shortest path length is proposed to reduce the average latency and increase the throughput of NoC. Finally, the routing algorithm is implemented in Verilog HDL, and performance evaluation is conducted by simulation. The results show that, compared with the non-congestion-aware routing algorithms, the proposal reduces the average delay  by 13.9% and 159% respectively, and increases the throughput by 21.6% and 16.8%, respectively under the two experimental scenarios (different packet count, and different packet inject rate) in a 16×16 2D mesh NoC.

Key words: neuromorphic, network on chip, Hamilton path, routing algorithm, congestion-aware