Abstract: This paper introduces the international mainstream cryptographic algorithms AES and SHA, and summarizes the development status of cryptographic algorithm instructions in the current mainstream general processor architecture. In order to improve the performance of general purpose processor in the field of cryptographic security, an extended instruction set of AES and SHA cryptographic algorithm for general purpose processor is designed, and an instruction execution unit of AES and SHA cryptographic algorithm that can be fully pipeline execute are realized, evaluated and optimized. The operating frequency of the instruction execution unit can reach 2.0 GHz, the total area is 17 644 μm2, and the total power consumption is 59.62 mW. Compared with the software implementation with the gene- ral instructions, the minimum speedup for AES cryptographic algorithm is 8.90 times, the minimum speedup for SHA cryptographic algorithm is 4.47 times and its speedup can reach 19.30 times in the case of fully pipelined execution of instructions, which significantly improves the performance of the processor in executing AES and SHA cryptographic algorithms, It is expected to be applied to general purpose processors and further enhance the competitiveness of general purpose processor chips in the field of cryptographic security applications. In addition, the cryptographic algorithm instruction execution unit can also be encapsulated into an IP specially used to support cryptographic algorithm and applied to a special chip in the field of cryptographic security. 

Key words: general purpose processor, advanced encryption standard(AES), secure hash algorrithm(SHA), cryptographic algorithm, cryptographic algorithm instruction, processor performance