| [1] |
ZHANG Yu er, XI Yuhao, LIU Peng.
Designing and optimizing RISC-V instruction set functionality based on multi-operand acceleration
[J]. Computer Engineering & Science, 2025, 47(6): 968-975.
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| [2] |
ZHANG Weiwei, CHEN Hu.
A multi-threaded interrupt-free RISC-V processor for low-latency acceleration component control
[J]. Computer Engineering & Science, 2025, 47(5): 787-796.
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| [3] |
PENG Lin, ZHANG Peng, CHEN Junfeng, TANG Tao, HUANG Chun.
Selection of sparse matrix multiplication algorithms based on supervised learning
[J]. Computer Engineering & Science, 2025, 47(3): 381-391.
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| [4] |
LIAN Zihan, HE Weifeng.
High-performance processor design based on dynamic timing slack exploitation
[J]. Computer Engineering & Science, 2025, 47(2): 219-227.
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| [5] |
ZHANG Zong-mao, DONG De-zun, WANG Zi-cong, CHANG Jun-sheng, ZHANG Xiao-yun, WANG Shao-cong.
Performance evaluation and analysis of vectorized SpMV algorithm based on scratchpad memory
[J]. Computer Engineering & Science, 2024, 46(9): 1521-1528.
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| [6] |
ZHOU Zhi, GAO Jian-hua, JI Wei-xing.
Optimization of sparse matrix-vector multiplication based on FPGA and row folding
[J]. Computer Engineering & Science, 2024, 46(8): 1340-1348.
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| [7] |
JIANG Jing-fei, HE Yuan-hong, XU Jin-wei, XU Shi-yao, QIAN Xi-fu.
NM-SpMM:A semi-structured sparse matrix multiplication algorithm for domestic heterogeneous vector processors
[J]. Computer Engineering & Science, 2024, 46(7): 1141-1150.
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| [8] |
SHI Yu, DONG Pan, ZHANG Li-jun.
An irregular sparse matrix SpMV method
[J]. Computer Engineering & Science, 2024, 46(7): 1175-1184.
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| [9] |
WANG Jie, FU Dan-yang, .
ROB compression method based on RISC-V superscalar processor
[J]. Computer Engineering & Science, 2024, 46(7): 1185-1192.
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| [10] |
WEI Yi, YANG Zhi-jie, TIE Jun-bo, SHI Wei, ZHOU Li, WANG Yao, WANG Lei, XU Wei-xia.
A multistage dynamic branch predictor based on Hummingbird E203
[J]. Computer Engineering & Science, 2024, 46(5): 785-793.
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| [11] |
WANG Yu-hua, HE Jun-fei, ZHANG Yu-qi, XU Yue-zhu, CUI Huan-yu.
DRM: A GPU-parallel SpMV storage format based on iterative merge strategy
[J]. Computer Engineering & Science, 2024, 46(3): 381-394.
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| [12] |
LI Fei, GUO Shao-zhong, ZHOU Bei, SONG Guang-hui, HAO Jiang-wei, XU Jin-chen.
Performance optimization of RISC-V basic math library
[J]. Computer Engineering & Science, 2023, 45(9): 1532-1543.
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| [13] |
SUN Cai-xia, SUI Bing-cai, DENG Quan, ZHENG Zhong, NI Xiao-qiang, WANG Yong-wen.
A hybrid ISA processor compatible with RISC-V at application level
[J]. Computer Engineering & Science, 2023, 45(8): 1347-1353.
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| [14] |
LI Xiao-ling, FANG Jian-bin, MA Jun, TAN Shuang, TAN Yu-song.
Automated task allocation of sparse matrix computation based on supervised learning
[J]. Computer Engineering & Science, 2023, 45(5): 782-789.
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| [15] |
ZHOU Li, ZHAO Zhi-qiao, PAN Guo-teng, TIE Jun-bo, ZHAO Wang.
RISC-V based design of graph convolutional neural network accelerator
[J]. Computer Engineering & Science, 2023, 45(12): 2113-2120.
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