Abstract: Taking the verification of a domestic multi-processor system as an example, based on the Transaction Based Verification (TBV) technology, this paper proposes and implements an automatic error tracking and positioning technology that can be applied to simulation verification. Through the transaction-level modeling of the processors specific functional process, various related request responses, memory access addresses and data streams in the verification environment, the transaction-level information library generated by the verification environment is recorded and generated. Based on the above information, the algorithm realizes the automatic tracking and positioning of the errors, which significantly shortens the error positioning time and improves the debugging efficiency of the simulation verification in the multi-processor system. Based on TBV, verifiers can describe the coverage points of Cache consistency with complex processes at a higher level than the design components. This transaction-level coverage description can compensate the deficiency that the original code coverage and functional coverage are limited to the module and component level, and is useful for comprehensiveness and sufficiency of verification.

Key words: processor verification, transaction based verification, multi-processor system, cache coherence, coverage, error tracing