Abstract: The stateful logic based on memristor is an effective way to break the "von Neumann bottleneck" and realize the Processing In Memory (PIM). However, the current research on stateful logic circuits in memory is mostly based on two-dimensional memristor memory array, and there is a lack of discussion on the implementation of stateful logic in more complex three-dimensional memristor memory array. Compared with the planar two-dimensional array, three-dimensional memristor array has greater storage density and richer device connectivity, which may provide a more flexible matching method for the constructing the stateful logic gates. Therefore, it is necessary to discuss the cascading and achieving process of stateful logic gates in three-dimensional memristor array. In this work, based on the planar stacked 3D memristor array, we study the implementation of complex stateful logic computing process from two aspects: the implementation of basic stateful logic gates and the integrated mapping method supporting cascade. Firstly, the connection relationship of devices in planar stacked 3D memristor arrays is analyzed and summarized. Based on this, the matching requirement of stateful logic gate for two-input Boolean logic is obtained. Secondly, a compound state logic gate is proposed. Logic inputs and logic output shares the same memristor, which can realize a complex logic function in one step (for example, defined as ONOR). It saves the number of steps and devices in complex stateful logic calculation process. Finally, an automatic synthesis mapping method based on complex stateful logic calculation in 3D memristor arrays is presented. Test results on the LGsynth91  benchmark show that, compared with the optimal mapping results in the current two-dimensional array, the proposed comprehensive mapping method based on the three-dimensional memristor array achieves the logic calculation between layers, and saves 41.1% of the used area of the array. After the introduction of the ONOR compound gate, the logical operation steps, the number of memristors and the used area of the array are further reduced by 8.6%, 18.8% and 50.5%, respectively.

Key words: memristor, in-memory computation, three-dimensional array, stateful logic, synthesis, mapping