Abstract: With the rise of artificial Intelligence, neural network algorithms used in various scenarios are developing vigorously and ever-changing. This makes the general edge deployment acceleration design of various algorithms represented by convolutional neural networks a big problem. In view of this situation, based on the principle of data correlation and Roofline model, a general and universal design rule is proposed to design hardware-paralleled convolutional neural network. The three most important parts such as the convolution layer, the pooling layer and the full connection layer are optimized. Based on the optimized modules, various convolutional neural networks can be built according to the requirements of application scenarios, so as to achieve universal design. With LeNet-5 network as the verification object and MNIST test set as the benchmark, the verification was carried out on XILINX ZC702 and XILINX ZC706 FPGA platforms. The interactive recognition system constructed based on high-level synthesis after optimization of each layer achieves 95.09% accuracy and 4.1 ms/ sheet reasoning speed on XILINX ZC702 platform, and the same accuracy and 0.997 ms/sheet reasoning speed on XILINX ZC706 platform. Both have very high processing speed.  

Key words: neural network, hardware acceleration, universal design, FPGA, high-level synthesis, Roofline, data correlation