Abstract: Standard cell library is the foundation of chip design, analysis, and verification, and its generation requires a lot of time and server resources. Therefore, vendors often only provide standard cell libraries under a few corners. However, the design of chip performance, power consumption, and reliability requires delay information of standard cells under multiple voltages, temperatures, and parameters (such as drive strength, channel length, and threshold voltage). To quickly and accurately calculate the delay of standard cells under multiple corners, this paper proposes a machine learning-based method for multi-voltage, multi-temperature, and multi-parameter standard cell delay calculation. By studying the factors that affect the delay of standard cells in depth, data sets are extracted from the 28nm process standard cell library and timing reports. Machine learning algorithms are used to train and calibrate the standard cell delay calculation model. The establishment of the model takes only a few minutes, which is much less than the time consumed by simulation methods (usually hundreds of hours). The average calculation error of the model is 1.542 ps for unknown voltage cell delay, 1.814 ps for unknown temperature cell delay, and 2.202 ps for cell delay under different parameters. The prediction error of cell delay in the static timing analysis process is less than 3%. This method can quickly and accurately calculate the delay of standard cells in real-time and can be applied to fast timing analysis under multiple scenarios before sign-off.

Key words: electronic design automation, standard cell library, gate delay calculation, machine learning