Abstract: Efficient, high-bandwidth, and high-reliability transmission protocols are crucial for Chiplet heterogeneous integration technology. Therefore, a parallel transmission interface protocol for Chiplet interconnection is proposed. A new hierarchical architecture is adopted to improve the flexibility and compatibility of the protocol. The fault tolerance to physical link failures is improved by using redundant channels based on the multi-path selection chain, and cyclic redundancy check is implemented in hardware to enhance the transmission reliability of the protocol. To verify the proposed transmission protocol, the protocol transmission path is implemented on two VC709 FPGAs. The experimental results show that compared with PCIe, the protocol has the advantages of high bandwidth, small interface area, and high reliability.

Key words: chiplet, interconnection protocol, high-bandwidth, high-reliability