Abstract: Networks-on-Chip (NoC) has become the standard paradigm for interconnect networks in multi-core processors. However, as the power supply voltage gradually decreases and the process size is reduced, the probability of soft errors in NoC increases. Error correction codes are commonly used in NoC router designs to tolerate soft errors. However, traditional router designs often only use Hamming codes for error correction, which has the problem of insufficient error correction capability, despite its simple design structure. This paper proposes a hybrid-hardening NoC router design based on error correction codes. The core idea of this design is to adopt different fault-tolerant code designs based on the importance of information bits, thus achieving a balance between router reliability and fault-tolerant overhead. Experimental results show that our design improves system reliability compared to the baseline design under synthetic traffic and PARSEC benchmark, and the hardware synthesis results also show that this design can shorten the critical path delay by 4%. 

Key words: soft error, hybrid hardening, networks-on-chip