Abstract: In recent years, the speed difference between processors and memories has become increasingly larger with the development of integrated circuit technology, and memories have increasingly become the bottleneck that limits the performance of computing systems. For DSPs in embedded and low-power consumption areas, their architectures and application scenarios are different from general-purpose CPUs, and the memory access design of CPUs cannot meet the memory access requirements of DSPs. To address the requirements of Very Long Instruction Word (VLIW) DSPs in terms of real-time memory access, order and fixed delay, and efficient data consistency, a scalar memory access unit suitable for DSPs is designed. The configurable design can meet the real-time memory access requirements of DSPs. The ID-based ordering mechanism ensures the order and fixed delay requirements of VLIW with a storage overhead of 87.5 B. The write back operation, designed for data consistency, is accele- rated by searching leading-one in hardware. The time consumed by the optimized write back operation are 26.4%, 51.3% and 76.2%, compared to the basic overhead of the progressive scan method, when 25%, 50% and 75% lines of the cache need to be written back. The consistency write back performance is proportional to the number of lines under concern, regardless of the cache capacity.

Key words: scalar memory access unit, digital signal processor (DSP), very long instruction word (VLIW)