Abstract: Changes in the instruction set architecture will result in changes in the processor hardware platform, and binary applications compiled for the old hardware platform will not be able to continue running on the new hardware platform. In this paper, a hybrid instruction set architecture compatible with multiple instruction sets at application level is proposed, and the processor based on the hybrid instruction set architecture can natively run multiple instruction set applications, which can effectively avoid the repetitive work of program developing and porting or the performance loss of the binary translation execution. Based on a self-developed processor, a hybrid instruction set processor compatible with RISC-V at application level is implemented. Compared with a single instruction set, the hardware overhead of supporting for two instruction sets at application level is only increased by 0.45%. The FPGA prototype system successfully boots the operating system ported to the hybrid instruction set architecture, and can correctly run the application based on each instruction set, which verifies the feasibility of the hybrid instruction set architecture idea. Under RISC-V instruction set, the processor achieves 5.58/MHz for Coremark, 8.44/GHz for SPECint2006 and 10.75/GHz for SPECfp2006.

Key words: hybrid ISA, RISC-V, processor, application level, compatible