Abstract: This paper designs a fast, scalable and accurate architecture simulator (MVSim) for VLIW multi-core vector processors. The scalable VLIW multi-core vector processor model, multi-level storage architecture model and multi-core performance model are designed in MVSim. It implements cycle-accurate simulation of instruction set architectures, efficient functional simulation of Cache, DMA and multi-core synchronization, and uses multi-threading to achieve efficient and scalable simulation of multi-core processors. The experimental results show that MVSim can accurately simulate the program execution of the target multi-core processor, the simulation results are completely correct, and it has good scalability. The average simulation speed of MVSim is 227 times and 5 times faster than RTL simulator  and CCS, respectively, and the average performance error is about 2.9%.

Key words: architecture simulator, VLIW, multi-core vector processor model, performance model, cycle-accurate simulator