MVSim: A fast, scalable and accurate architecture simulator for VLIW multi-core vector processors

Computer Engineering & Science ›› 2024, Vol. 46 ›› Issue (02): 191-199.

• High Performance Computing • Previous Articles Next Articles

MVSim: A fast, scalable and accurate architecture simulator for VLIW multi-core vector processors

LIU Zhong1,2,LI Cheng1,2,TIAN Xi1,2,LIU Sheng1,2,DENG Rang-yu1,2,QIAN Cheng-dong3

（1.College of Computer Science and Technology,National University of Defense Technology,Changsha 410073;
2.Key Laboratory of Advanced Microprocessor Chips and Systems,Changsha 410073;
3.Tianjin Advanced CPU Enterprise Key Laboratory,Tianjin 300000,China）

Received:2023-09-01 Revised:2023-10-27 Accepted:2024-02-25 Online:2024-01-25 Published:2024-02-24

Abstract

Abstract: This paper designs a fast, scalable and accurate architecture simulator (MVSim) for VLIW multi-core vector processors. The scalable VLIW multi-core vector processor model, multi-level storage architecture model and multi-core performance model are designed in MVSim. It implements cycle-accurate simulation of instruction set architectures, efficient functional simulation of Cache, DMA and multi-core synchronization, and uses multi-threading to achieve efficient and scalable simulation of multi-core processors. The experimental results show that MVSim can accurately simulate the program execution of the target multi-core processor, the simulation results are completely correct, and it has good scalability. The average simulation speed of MVSim is 227 times and 5 times faster than RTL simulator and CCS, respectively, and the average performance error is about 2.9%.

Key words: architecture simulator, VLIW, multi-core vector processor model, performance model, cycle-accurate simulator

LIU Zhong, LI Cheng, TIAN Xi, LIU Sheng, DENG Rang-yu, QIAN Cheng-dong. MVSim: A fast, scalable and accurate architecture simulator for VLIW multi-core vector processors[J]. Computer Engineering & Science, 2024, 46(02): 191-199.

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MVSim: A fast, scalable and accurate architecture simulator for VLIW multi-core vector processors

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