• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

Computer Engineering & Science ›› 2024, Vol. 46 ›› Issue (02): 200-208.

• High Performance Computing • Previous Articles     Next Articles

Design and implementation of agile switching chip for equipment platform

LIU Ru-lin,YANG Hui,LI Tao,L Gao-feng,SUN Zhi-gang   

  1. (College of Computer Science and Technology,National University of Defense Technology,Changsha 410073,China)
  • Received:2023-09-12 Revised:2023-10-22 Accepted:2024-02-25 Online:2024-01-25 Published:2024-02-24

Abstract: When building network systems for equipment platforms such as vehicles, ships, and aerospace, comprehensive consideration needs to be given to constraints such as function, performance, volume, power consumption, and ease of use. Traditional high performance commercial network switching chips have high power consumption and complex configuration and use, making them difficult to meet relevant needs. Therefore, a programmable and low power agile switching chip architecture is proposed for equipment platforms. This architecture introduces protocol-independent ultra-long content matching-action pipelines to provide programmable forwarding configurations, flow rate limiting, packet modification and other functions, and supports various existing network protocols as well as user-defined protocols. The architecture provides flexible management and configuration modes to meet various application requirements such as remote configuration and lightweight configuration without management CPUs. In addition, through the expansion function of the agile switching protocol, the lookup results, action processing records, user configuration information, etc. can be sent out of the chip along with the original packet to achieve fine-grained processing and flexible function expansion at the individual packet level. Based on the agile switching architecture, the YHHX-DS160 agile switching chip has been taped out. This chip can provide full interface line speed switching capability of 160 Gbps, with a maximum power consumption of only 6.6 W, achieving an energy efficiency ratio of 24 Gbps/W.

Key words: switching chip, protocol-independent, match-action pipeline, low power, equipment platform