Abstract: RISC-V instruction set has the advantages of flexibility and scalability, and vector extension is one of its extended instruction sets. When implementing vector extention, it is necessary to split the vector instruction into multiple microinstructions. If each microinstruction occupies a reordering buffer (ROB) entry, there will be certain information redundancy, and will reduce the number of instructions executed in parallel (in-flight instructions) in the CPU, affecting processor performance. Based on the method of decoupling the storage of instructions and microinstructions in ROB, a new queue RAB is used to store information such as the renaming mapping relationship of the destination register of each microinstruction, and each ROB stores only the common information of the microinstructions derived from its corresponding instruction. ROB and RAB respectively control the commit and walk of instructions and microinstructions, which reduces the redundancy of stored information and alleviates the problem caused by too many microinstructions for vector instruction splitting. On the basis of the above method, this paper implements the ROB compression of scalar instructions at the same time, increasing the maximum number of in-flight instructions with the same number of ROB entries. The final simulation results show that this method effectively improves the performance of the processor.

Key words: RISC-V, superscalar, processor, ROB compression