Abstract: The high-speed serial interface chip is an important IP in high-performance interconnect network communication. This paper proposes a DSP design for 56 Gb/s high-speed Serdes receivers, in response to the problem of high bit error rate caused by severe channel attenuation over long transmission distances in high-performance interconnect network backplane communication using 56 Gb/s four pulse amplitude modulation (PAM4) signals. The DSP adopts a 64-channel parallel structure and processes the digitized signal from the receiver through a 16-Tap feed forward equalizer (FFE) and a decision feedback equalizer (DFE). By using the K-means clustering algorithm to generate dynamically changing DFE decision levels and combining it with the least mean square (LMS) algorithm, it can handle the equalization problem under different channel attenuation of 15~35 dB. To verify the performance of the algorithm, an experimental verification platform based on analog frontend chips and field programmable gate arrays (FPGA) was constructed. The experimental results indicate that the channel attenuation is 15~35  dB@14 GHz at a speed of 56  Gb/s, the error rate is less than 5e-10.

Key words: K-means algorithm, feed forward equalization, decision feedback equalization, adaptive equalization