Abstract: Sparse matrix-vector multiplication (SpMV) is a key kernel in scientific and engineering computing. Due to the irregular data distribution in sparse matrices and the irregular memory access operations in SpMV calculations, the performance of SpMV on multicore CPUs and GPUs still lags significantly behind the theoretical peak performance of these devices. Existing CPUs and GPUs are limited in their architectures, making them unable to effectively utilize the special structure of sparse matrices to accelerate SpMV calculations. However, Field-Programmable gate arrays (FPGA) can achieve efficient parallel computing through customized circuits, which better handle the computation and storage issues of sparse matrices. An SpMV optimization method based on FPGA is proposed, which utilizes a high-level synthesis streaming processing engine and employs an adaptive multi-row folding SpMV optimization strategy. This method reduces the ineffective storage and computation of zero elements in the processing engine through row folding, thereby enhancing the performance of FPGA-based SpMV calculations. Experimental results show that compared to existing FPGA implementations, the proposed row folding-based dataflow engine achieves a maximum speedup of 1.78 times and an average speedup of 1.15 times.

Key words: sparse matrix-vector multiplication, field-programmable gate array, high-level synthesis, row folding