Computer Engineering & Science ›› 2024, Vol. 46 ›› Issue (08): 1390-1394.
• High Performance Computing • Previous Articles Next Articles
ZHOU Lin-ning,LIU Jie,LI Hong-kui,FU Hao-dong,LIU Hong-hai,XIAO Hao
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Abstract: Although the Store instruction backtracking strategy adopted by BOOM processors solves the problem of data conflicts caused by out-of-order execution of memory access instructions, this strategy can lead to a large amount of pipeline flushing and reduce the processor performance. To address this, a correlation prediction method for memory access instructions is proposed. This method cancels the query operation before the Load instruction accesses memory and adds a Load instruction correlation prediction table. Only Load instructions that are predicted to be uncorrelated can be executed in disorder. This method avoids a large amount of pipeline flushing while ensuring the correctness of program logic. The test program uses 7 subroutines under SPEC CPU 2006, and the experimental results show that the improved processor's execution performance is improved by 3.5% on average.
Key words: out-of-order execution, memory access instruction, correlation prediction
ZHOU Lin-ning, LIU Jie, LI Hong-kui, FU Hao-dong, LIU Hong-hai, XIAO Hao. Optimization of memory access logic in BOOM processor[J]. Computer Engineering & Science, 2024, 46(08): 1390-1394.
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URL: http://joces.nudt.edu.cn/EN/
http://joces.nudt.edu.cn/EN/Y2024/V46/I08/1390