Abstract: High-speed serial interfaces serve as the interconnect core between chips in high performance computer systems. Addressing the high bandwidth requirements for high-speed serial communication, the design and simulation of a 56 Gbps Duobinary signal clock and data recovery (CDR) circuit were completed based on Verilog-AMS on the Candence platform. Multi-level transmission can reduce the demand for bandwidth. The CDR circuit was designed using a phase interpolator (PI), with the phase detection results from a Bang-Bang phase detector serving as the basis for phase discrimination. Digital signal processing (DSP) algorithms, including a voting algorithm, filtering algorithm, and phase control code conversion algorithm, were employed to process the phase detection results. The digital algorithms reduced the complexity of the circuit design, facilitated the adjustment of loop gain, improved system stability, and decreased loop delay. Simulation results demonstrate that the CDR circuit can track phase differences and frequency offsets of 100 PPM. By adding a 0.25 UI sinusoidal jitter to the input data, with a loop bandwidth of 23 MHz, the system can track the sinusoidal jitter when the jitter frequency does not exceed the loop bandwidth. The jitter tolerance meets the specifications of the CEI-56G protocol.

Key words: clock and data recovery (CDR), Duobinary signal, Bang-Bang phase detector, digital signal processing (DSP) algorithm, sinusoidal jitter