Abstract: With the development of integrated circuits and the continuous expansion of chip applications, configurable CPU facilitates the exploration of the chip design space. Configurable CPU can not only meet the demands of agile design but also cater to users’ needs for tuning based on target applications. However, at present, the performance tuning of application-specific configurable CPU still primarily relies on experienced architecture engineers, lacking a set of scientific methodologies for guidance. Therefore, this paper proposes a configurable CPU performance analysis method for specific applications. At the software level, the Perf tool is utilized to quickly identify hot code blocks in applications during hardware execution. At the hardware level, by analyzing two counting modes (counting of cycles and counting of slots) within the analysis framework, the hot execution conditions of each execution unit are pinpointed, enabling designers to swiftly locate hot behaviors in hardware execution. This paper conducts agile design for a configurable DMR (dual-module redundancy) architecture supporting the RISC-V instruction set using the typical fluid dynamics program NPB (NAS parallel benchmark). The experimental results indicate a 13.2% improvement in single-core performance of the configurable CPU, with a 12.2% increase in area overhead.

Key words: performance analysis, configurable CPU, performance monitoring unit(PMU), NAS parallel benchmark(NPB), test