Abstract: The memory consistency model, commonly referred to as the memory model, defines the observation rules for memory access in multi-core systems. As an architectural specification that both hardware and software must adhere to, it is characterized by difficulties of design, description, implementation, and testing, and has long been a research focus in both academic and industrial communities. Due to the uncertainty in the execution order of parallel programs, testing of memory models typically requires repeatedly running specific programs on a large scale. The presence of illegal memory access orders is determined based on the final program states. This process is particularly time-consuming during the pre-silicon simulation phase, posing significant challenges to chip verification. In recent years, RISC-V has gained widespread popularity due to its open-source nature, simplicity, modularity, and high customizability. Leveraging its open-source advantage, RISC-V chips offer an extremely high degree of flexibility in instruction set extension and micro-architecture design. Its memory model also allows customization on the basis of compliance with specifications, and this high customizability introduces additional challenges to chip verification. To address this issue, this paper proposes an efficient memory consistency testing method based on loop unrolling for the RISC-V architecture. By analyzing the performance bottlenecks of existing testing methods and drawing on the loop unrolling technique from traditional compilation, the method merges repeatedly executed test programs. This not only significantly reduces thread synchronization overhead but also increases the probability of inter-leaved memory access execution between threads, thereby improving testing efficiency. Experimental results show that, compared with existing memory consistency testing methods, the proposed method achieves a testing efficiency improvement ranging from 1.5 times to 184 times  across different platforms, including RISC-V boards and simulators.

Key words: memory consistency, RISC-V architecture, loop unrolling