Abstract: The instruction set architecture (ISA) serves as the foundational framework of a chip, yet existing research on its performance impact often relies on real hardware implementations. However, varying hardware setups pose challenges for direct comparison and analysis of ISAs. To address this issue, simulations of ARM, RISC-V, and x86 ISAs were conducted using the Gem5 simulator, using identical hardware configurations and the same compiler version,  thereby enabling a controlled comparative analysis. CoreMark, Dhrystone， and Whetstone are adopted as benchmark programs, while McPAT assesses power consumption. Results from the simulations reveal that the ARM ISA exhibits superior performance and lower power consumption compared to RISC-V and x86 ISAs. Although differences between ARM and RISC-V are marginal, the performance gap between ARM and x86 may stem from the relatively modest hardware configuration utilized, which could be mitigated or reversed through the adoption of more aggressive hardware techniques. This research underscores that while an ISA plays a pivotal role, solely relying on it cannot fundamentally enhance efficiency.

Key words: instruction set architecture(ISA), Gem5 simulator, microarchitecture power, area,and timing（McPAT） simulator, micro-architecture, simulation