Abstract: Compute-in-memory (CIM) is considered a promising solution to overcome the “memory wall” bottleneck, enhancing energy efficiency and area efficiency significantly. This paper proposes a novel digital SRAM-based compute-in-memory macro architecture. It optimizes power consumption and enhances chip energy efficiency by means of hybrid encoding of weight data and activation data. Additionally, a series of circuit-level optimizations are performed on the core adder tree circuit to improve the chip’s area efficiency. Under TSMC’s 28 nm process library, the proposed DCIM macro with hybrid encoding optimization improves energy efficiency by 2.17 times  at 0.9 V, 250 MHz, using the ResNet20 test model. The adder tree optimization reduces 14.2% area in the overall DCIM macro. Finally, a 256×64 DCIM achieves an energy efficiency of 20.83 TOPS/W when processing the ResNet20 model. 

Key words: artificial intelligence, SRAM, digital compute-in-memory, hybrid encoding, adder tree