Abstract: Conventional synchronous circuit design methods determine the operating frequency based on the critical path identified through static timing analysis. However, the critical path is not excited every cycle, leading to dynamic timing slack between the critical path and the actual activated path. Therefore, a high-performance processor design method based on instruction-level timing slack exploitation is proposed, aiming to maximize the exploitation of dynamic timing slack for performance improvement. An automated timing analysis platform is built to obtain instruction timing. A timing encoding strategy is designed to transmit timing information to the hardware through instruction encoding without increasing hardware overhead. Additionally, a timing decoding and arbitration circuit is designed at the hardware level to adjust the clock cycle accordingly based on the instruction timing encoding, thereby achieving instruction-level dynamic timing slack exploitation. Simulation verification of the proposed method is conducted on a superscalar processor based on the RISC-V instruction set. The results show that, compared to traditional design methods, this method can achieve a maximum performance improvement of 31%.  

Key words: timing slack, high-performance, processor, reduced instruction set computer-version five(RISC-V)