Abstract: A high-speed communication implementation scheme for AES based on FPGA is proposed. By splitting the encryption process into a 30-level parallel pipeline structure, communication speed and encryption efficiency can be improved. At the same time, based on the special GF (28) finite field operation rules of the MixColumn parts in AES and the structural characteristics of FPGA parallel operation, an intermediate cross-MixColumn structure is designed. This structure can effectively reduce the computational delay and usage area of MixColumn and inverse MixColumn parts, and improve the encryption efficiency. From the perspective of logical algebra, the differences in computational resource usage between traditional MixColumn structures, newer MixColumn structures, and inter-mediate cross computing structures are analyzed. Finally,  the verification results on Xilinx’s XC5VSX240T chip show that the proposed scheme achieves a throughput of 60.928 Gbps and an encryption efficiency of 14.875 Mbps/LUT.

Key words: FPGA, AES encryption algorithm, MixColumn, pipeline