Abstract: This paper aims to implement the application of a chaotic system in image encryption within field-programmable gate array (FPGA). Based on the improved Bao chaotic system, the chaotic system is discretized using the improved Eulers algorithm, and the hardware design is carried out using Verilog language. The accuracy of chaotic system at the software design level is verified through register transfer level (TRL) circuits and ModelSim timing simulation. Discretized chaotic sequences are utilized on the FPGA for image encryption and corresponding key decryption, and the feasibility of the encryption scheme is verified through a video graphics array (VGA) interface. This study successfully implements image encryption using chaotic system at the hardware level, laying the foundation for further application and implementation of chaotic encryption technology on FPGA.

Key words: chaotic system, FPGA implementation, Verilog design, image encryption