Abstract: With the rapid expansion of data volume in various application scenarios such as deep learning, the hardware overhead of communication and storage has significantly increased. Against this backdrop, the importance of compression methods has grown substantially. Huffman coding is one of the most representative and widely used compression methods, known for effectively compressing data and saving storage space without compro-mising data integrity. However, due to the limitations of hierarchical memory storage, traditional hardware solutions for Huffman coding face challenges of high latency and energy consumption. This paper proposes a hardware architecture named ReHuff, which leverages resistive random-access memory (ReRAM) to enable in-memory Huffman encoding, and  designs a ReRAM-based Huffman coding mapping method to extract valid data. To address the mismatch between variable-length encoded data and fixed-length ReRAM blocks during mapping, a dual-stage variable-length data selection and segmentation approach is proposed, adapting to the architectural design to integrate variable-length outputs, thereby reducing energy consumption and improving ReRAM utilization efficiency. Simulation results demonstrate that the proposed design out-performs representative benchmarks, improving performance by 18.6 times and reducing energy consumption by 82.4%.

Key words: Huffman coding, data compression, resistive random access memory, accelerator design, data mapping