Abstract: In the design of application-specific microprocessors, designers need to  iteratively  experiment with different architectural parameters to achieve optimal application support. Multi-port register files, as core components, still rely on full-custom design or traditional compiler-assisted design. However, these methods often struggle to balance high performance requirements with design flexibility, making it difficult to achieve co-optimization with the architecture. This paper proposes a physical compiler for multi-port register files, which can automatically and quickly generate register file circuits and layouts with specified capacity and port count. Additionally, this paper proposes an optimized port structure to enhance the parallel access performance of the register file and a performance-driven heuristic algorithm to achieve optimized placement and routing results. Experimental results show that the proposed compiler can generate register files in approximately  tens of hours to meet co-optimization requirements, achieving 31.5% speed improvement and 28.8% power reduction compared to full-custom designs, as well as 20.7% higher speed and 33.9% lower power consumption relative to traditional compiler-assisted designs.

Key words: multi-port register file, physical compiler, port optimization technique, heuristic algorithm, computer architecture