Abstract: Connecting multiple dies through Chiplet interconnect interfaces has become the mainstream of chip design in the post-Moore era.The Chiplet interconnection interface circuit is only used for interconnection of multiple Chiplets within a single package,with an extremely short transmission distance.In large-scale computing systems,multiple chips need to build larger-scale computing nodes.How to achieve long-distance interconnection of Chiplets in multiple chips at the board-level has become a very important issue.Intel and others have defined a Retimer  for Chiplet interconnection interfaces in the universal Chiplet interconnect (UCIe) specification,but the architectural details are not disclosed.The research on Retimer for Chiplet interconnection interfaces in China is still blank.Combining with the formulation of the independent Chiplet interconnection interface standard,this paper proposes a Retimer (D2C_Retimer) architecture for Chiplet interconnection to chip interconnection,which supports the conversion of the die-to-die (D2D) interface into a chip-to-chip (C2C) interface,realizing the interconnection of Chiplets across chips at the board level.Through key technologies such as the reliable transmission mechanism of Retimer,the credit mechanism of Retimer,and the hierarchical sideband transmission link,it not only achieves compatibility with the independent Chiplet interconnection standard,but also has advantages in credit management,reliable transmission,etc.Experiments show that the implemented Retimer can realize long-distance interconnection across packages between Chiplets without changing the existing independent interconnection standard,which is of great reference significance and engineering implementation value for improving the domestic Chiplet interconnection ecosystem.

Key words: Retimer, Chiplet, interconnection protocol, high-reliability