• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

Computer Engineering & Science ›› 2025, Vol. 47 ›› Issue (9): 1521-1534.

• High Performance Computing • Previous Articles     Next Articles

Research on multi-protocol support technology and standardization in Chiplet interconnection interface

HE Xingyang1,2,ZHOU Hongwei1,2,ZHOU Yuxuan1,2,SUN Yubo3,LI Mengjin1,2   

  1. (1.College of Computer Science and Technology,National University of Defense Technology,Changsha 410073;
    2.Key Laboratory of Advanced Microprocessor Chips and Systems,
    National University of Defense Technology,Changsha 410073;
    3.School of Computer Science and Technology,Changsha University of Science and Technology,Changsha 410114,China)
  • Received:2024-11-02 Revised:2024-12-04 Online:2025-09-25 Published:2025-09-22

Abstract: Chiplet integration has emerged as an effective approach to overcoming the limitations of chip fabrication, memory bandwidth, power consumption, and scalability in the post-Moore era. Establishing standardized Chiplet interconnection interfaces is a prerequisite for heterogeneous Chiplet integration, significantly simplifying Chiplet adaptation, improving the reusability of Chiplets and interconnect interfaces, and accelerating multi-Chiplet SoC design. Since different types of Chiplets adopt varying protocol standards at the protocol layer, Chiplet interconnection interface must support multiple protocols. To address this, we propose a multi-protocol support technology based on broad categorization, dividing protocols into two classes according to their packet characteristics: fixed-pattern protocols and stream-pattern protocols. This technology directly supports protocols conforming to these two categories, while indirectly supporting non-conforming packet types through a “native mode”. Additionally, it enables concurrent execution of any two protocols and provides enhanced support for CXL and UCIe. The technology improves indirect protocol support efficiency via micro-packet-level compatibility and achieves complete decoupling between the protocol and adapter layers by delegating link management information embedding in data payloads to the protocol layer. Based on this, we designed a Chiplet interconnection interface supporting concurrent PCIe and CXL.mc protocols and established a simulation verification environment. Experimental results confirm the feasibility and correctness of the proposed technology in multi-protocol support and concurrent protocol execution.

Key words: Chiplet integration, Chiplet interconnect specification, Chiplet interconnection interface, multi-protocol support technology, multi-protocol concurrency