Abstract: With the rapid development of computer technology, the volumes of data storage and computation are continuously increasing, making secure, reliable, and efficient data storage and transmission more important than ever. Among various encryption algorithms, the AES algorithm is a widely used symmetric encryption algorithm. The goal of this paper is to improve  AES algorithm to make it more suitable for hardware implementation, aiming to reduce hardware area   and enhance processing performance. Firstly, this paper proposes a lightweight AES algorithm (AES_ll) and designs four custom instructions based on the RISC-V instruction set architecture to improve the flexibility of the algorithm and reduce costs. Secondly, a dedicated AES_ll coprocessor is designed, and a verification platform capable of randomly generating plaintexts and corresponding ciphertexts is established to ensure the reliability and stability of the AES_ll hardware implementation under different inputs. Finally, synthesis is conducted under a 28 nm process. Experimental results show that the AES_ll coprocessor achieves a throughput rate of up to 2.976 Gbit/s, with an area of approximately 13.97 kgates, offering significant advantages in terms of the throughput-to-area ratio. The design provides an excellent solution for fields with limited resources and high demands for encryption and decryption.

Key words: AES algorithm, coprocessor, RISC-V, instruction extension