• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

Computer Engineering & Science ›› 2026, Vol. 48 ›› Issue (1): 98-107.

• Graphics and Images • Previous Articles     Next Articles

Research and implementation of a low-light image enhancement algorithm based on FPGA

XIAO Jian,LI Zhibin,YANG Jin,CHENG Hongliang,HU Xin   

  1. (1.School of Electronics and Control Engineering,Chang’an University,Xi’an  710064;
    2.Xi’an North Electro-optic Science & Technology Defense Co.,Ltd.,Xi’an 710043,China)
  • Received:2024-01-08 Revised:2024-08-11 Online:2026-01-25 Published:2026-01-25

Abstract: To address the issues of high computational complexity, difficulty in achieving real-time performance, and other challenges associated with implementing low-light image enhancement algorithms using software methods such as deep learning, this paper presents an improved Retinex-model-based low-light image enhancement algorithm that is readily deployable on FPGAs. The algorithm begins by converting the input low-light image from the RGB color space to the YCbCr color space. The Y component in this space is then selected as the initial illuminance component and processed with adaptive Gamma correction and bilateral filtering. This process enhances the brightness of the initial illuminance component while simultaneously achieving noise reduction and detail enhancement in the image. Subsequently, the enhanced image is generated based on the Retinex model. The enhanced image is then converted back to the YCbCr color space, where the Y component undergoes multi-scale detail enhancement before being transformed back to the RGB color space as the final enhanced output. Experimental results demonstrate that when comparing the output images of the proposed low-light image enhancement algorithm deployed on an FPGA with those obtained through algorithm simulation on  MATLAB, the structural similarity index measure (SSIM)  is close to 1, making it difficult to distinguish between the two with the naked eye. At a clock frequency of 200 MHz, the algorithm processes a 1 280×720 resolution image in approximately 21 ms. Furthermore, when deployed on a domestic FPGA model, the proposed algorithm exhibits low resource utilization and consumes only 3.357 W of power, meeting low power requirements and demonstrating significant  practical and engineering application value.


Key words: image enhancement, field programmable gate array(FPGA), adaptive gamma correction, bilateral filtering, multi-scale detail enhancement