Abstract: Nowadays, numerous intellectual property (IP) cores are integrated into complex system-on-chip (SoC) designs. These IP modules vary in types, involving different data widths, operating frequencies, and traffic patterns. Typically, these IP modules are interconnected via network-on-chip(NoC) with regular topological structures. However, such traditional structures may lead to link load imbalance and redundancy, thereby affecting performance and overhead. Although customizing topologies has emerged as effective solutions for optimizing domain-specific NoCs, they require designers to possess profound expertise and entail substantial design iteration time. This paper proposes a framework for generating custom topologies for domain-specific NoCs. Based on hardware configurations, traffic demands, and design objectives, this framework employs a rapid topology  design exploration method to automatically generate optimized topologies. The framework first transforms topology factors into a combinatorial optimization problem through architectural analysis. Subsequently, it introduces a traffic-balanced grouping method to accommodate large-scale NoC design exploration. Finally, it utilizes an improved hierarchical ranking approach to achieve multi-objective optimization. Experimental results demonstrate that the framework rapidly generates topologies tailored to different requirements. Compared to regular topologies, the topologies generated by this framework can enhance bandwidth performance by at least 75% or reduce area overhead by 26% for specific domain-specific SoCs.

Key words: custom network, flow analysis, network-on-chip (NoC), topology generation