Abstract:

In the current ASIC functional verification flow, the debuggability for FPGA-prototype verification systems is a main obstacle that restricts the veri fication speed. A new simulated memory technology is provided in this paper. In this technology, memory accesses in the FPGA board are mapped to a PC and simulated by software. Functional verification engineers can record and analyze the executing track of test use cases,and set the breakpoints of the m emory access transactional level conveniently, which greatly improves the debuggability of the verification board. Meanwhile, the complexity and cost of  simulated memory are lower than actual hardware with a large memory system, which is helpful to decrease the complexity of the FPGA-prototype verification board.

Key words: （ASIC, FPGA, simulated memory, functional verification）