Abstract:

For digital processing processors with the Very Long Instruction Word （VLIW） architecture, a significant amount of power is consumed in instruction   memories. According to the characteristics of digital processing applications, loop buffering can be used to reduce the power consumption of instruction   memories while fetching instructions. This paper presents a low power compilation method based on the compiler-controlled loop buffer where the compile r is responsible for selecting appropriate loops and putting them into the buffer. The paper gives an analysis of the power dissipation and architectura l design of the loop buffer, and a compilation method to use the loop buffer effectively. Finally, the effectiveness of the proposed method is validated by a function-level power analysis model.

Key words: （compiler, loop buffering, low power）