• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

J4 ›› 2011, Vol. 33 ›› Issue (3): 28-33.doi: 10.3969/j.issn.1007130X.2011.

• 论文 • Previous Articles     Next Articles

An I/O Restricted Parallel Speedup Model  and the Scalable I/O Architecture

LI Qiong,DU Yunfei,YANG Xuejun   

  1. (School of Computer Science,National University of Defense Technology,Changsha 410073,China)
  • Revised:2009-04-14 Online:2011-03-25 Published:2011-03-25

Abstract:

The effective solutions for the I/O bottleneck can be found from the following six levels, including applications, algorithms, languages and compilers, runtime libraries, operating systems, and I/O architecture. Among all the levels mentioned above, the I/O architecture is the most fundamental. In order to meet the I/O requirements and challenges, along with our research task of a high performance parallel computing system, this paper presents a theoretical study of I/O architectures, from which we can make it possible the high performance and scalability in terms of I/O architecture level. The current parallel I/O performance analysis lacks scientific theoretical models to support the I/O architecture design. The paper studies the impact of I/O workload on the scalability of parallel computing systems and proposes an I/O restricted parallel speedup model. Based on this model, which can be used to guide I/O architecture design, a scalable parallel I/O architecture for high performance computing is presented. Moreover, the paper analyzes several strategies for improving the system scalability, which serves as the basis for further study.

Key words: high performance computing;I/O architecture;parallel speedup model