Abstract:

A highspeed lowpower memory readandwrite control circuit is analyzed. In the circuit a latchbased sense amplifier is used and the input of the amplifier is connected to the bit lines of the memory through isolation transistors. Tradeoff can be made between the read delay, power dissipation and read reliability of a memory by controlling the timing of the isolation transistor and the sense amplifier. The simulation results in this paper will be useful for memory designer.

Key words: memory;low power;sense amplifier;differential bit line;isolation circuit