Abstract:

Reliability has become a key issue of NetworksonChip (NoC) as the technology scales down to the nanoscale domain. In this paper, we design and implement a faulttolerant deflection router based on reinforcement learning for NoC. The router reconfigures the routing table through a reinforcement learning method during packet transmission to achieve faulttolerance. An optimized router with 2 pipeline stages is also implemented to improve the performance of the router. The synthesized results under the TSMC 65〖WTBX〗nm〖WTBZ〗 technology show that the router with 2 pipeline stages can achieve the frequency of 750MHz, which is almost 1x more than that of the original router, while the area only increases by 22%. The simulation results under the synthetic workloads demonstrate that the average network latency of the router with 2 pipeline stages is less than that of the router with no pipeline.

Key words: networksonchip;faulttolerant;deflection routing;performance optimization