Abstract:

In highspeed SerDes with the half rate structure, the duty of the clock is seriously important, which is the decisive factor for unit intervals. In this article, a 1.25GHz ring oscillator PLL is established on the 0.13μm CMOS process, in which a duty balance circuit is integrated. The result of testing shows the stable output clock is 1.25GHz, and the duty is within the range of 49.86～51.21%, and the mean duty is 51.21%.

Key words: halfrate;SerDes;PLL;duty balance;coupling phase adjustment