Abstract:

Blockmatching based motion estimation is one of the most important techniques in image and video applications. The sum of absolute difference (SAD) is the major computation in motion estimation and requires huge computation complexity and transmission bandwidth. This paper proposes a reconfigurable SAD accelerator, in which a 16×1 processing elements (PE) array and an adder tree structure are used to improve the execution speed of SAD computation. The pipeline partition of PE array and adder tree is performed carefully in order to increase the work frequency. In order to reduce the performance loss caused by data transfer delay, a DMA event mechanism is employed to transmit data when the SAD accelerator is working. The experimental results show that, the proposed architecture needs 4102 cycles for searching a 16×16 search window. With a 0.13μm CMOS standard cell technology, the proposed accelerator requires only 16.8 k gates and 3.5 KB of memory at the 750MHz operation frequency.

Key words: motion estimation;BMA;processing element array;video coding