Abstract:

With the technology scaling down,relative to the gate delay, the global wire delay increases and hence a flit transmission between routers requires several cycles on NetworkonChips(NoCs).Registers in pipelined channels cannot buffer flits when the congestion occurs in the creditbased flow control scheme.Therefore,an adaptive Channel Double Buffer (CDB),which can buffer flits,is proposed in the paper. With detailed design and analysis of the gatelevel circuit, the delay model of the CDB is derived based on the theory of the logical effect.It is validated by Synopsys Prime Time in a TSMC 65 nm technology and found the difference within one τ4.Experimental results show that the depth of the CDB is the same with the SPLS for a 1mm semiglobal interconnect wire in a 32nm technology.

Key words: networkonchip;channel double buffer;delay model