Abstract:

With the development of integrated circuit technology, chip performance is increasing, time to market is becoming shorter, chip verification is a key component of the chip design and is used in the entire design process, so the efficiency and quality of verification directly determines the success or failure of the chip. The design and implementation process of coveragedriven function verification is presented, it is more efficient to use PSL languages designed as assertion monitors to describe system behavior, the simulator tests these assertion monitors, and generate warnings or errors if an assertion fails, monitors will quickly identify when the protocols or sequences of signals are incorrect. This approach is used in a network interface chip design. It reduces the complexity, and improves the speed and quality of verification. Coverage dates are used to estimate the verification process, integrality and correctness of test bench, this method increases the design efficiency.

Key words: coveragedriven;function verification;PSL(property specification language);SystemVerilog