J4 ›› 2016, Vol. 38 ›› Issue (06): 1071-1077.
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SHEN Jianliang1,2,LI Sikun2,WANG Guanwu2,L Ping1,LIU Lei2,LIU Qinrang1
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Abstract:
Since the traditional design methods of MPSoC have large design exploration space and high design complexity, we propose a coarse grain reconfigurable SoC design method based on architecture template. The architecture template can be reused, and its parameters can be configured, so the method can reduce the design exploration space, and improve the design efficiency and computational performance. The design templates are instantiated, and a cryptographic applicationspecific multireconfigurable instruction sets processor SoC(MultiRISP SoC) is constructed. Experimental results show that the performance of the MultiRISP SoC is equivalent to several typical reconfigurable platforms, but its system is more efficient.
Key words: architecture template;multicore SoC system architecture;coarse grain reconfigurable SoC
SHEN Jianliang1,2,LI Sikun2,WANG Guanwu2,L Ping1,LIU Lei2,LIU Qinrang1. A coarse grain reconfigurable SoC design method based on architecture template [J]. J4, 2016, 38(06): 1071-1077.
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http://joces.nudt.edu.cn/EN/Y2016/V38/I06/1071