Computer Engineering & Science
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ZHANG Kun,LIU Xiao,ZHENG Fang,XIE Xiang-hui
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Manycore processor design faces a great challenge in terms of chip area utilization. How to improve the proportion of the computing units in the limited chip area is a hot topic in the research on manycore architecture. We focus on the design of the instruction cache on the manycore processor. The instruction cache is shared among several processing cores in order to improve the pipeline performance. We propose a design of shared instruction cache and implement cycleaccurate performance simulation on it. The RTL codes of the shared instruction cache are synthesized to get the area cost and timing results. Experimental results demonstrate that the shared instruction cache can decrease 11% to 27% miss rate and improve the pipeline performance by 4% to 7%.
Key words: many-core processor, instruction cache, architecture optimization
ZHANG Kun,LIU Xiao,ZHENG Fang,XIE Xiang-hui. Shared L1 instruction cache for manycore processors[J]. Computer Engineering & Science.
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URL: http://joces.nudt.edu.cn/EN/
http://joces.nudt.edu.cn/EN/Y2017/V39/I05/834