Traditional processor pipeline is a branch-instruction-centric design where a large number of chip resources are used to improve the prediction accuracy of branches. We present a load-centric core pipeline design in array many-core processors. In the load-centric pipeline, the load instruction has higher priority to be issued and executed. Besides, we also propose a prediction mechanism to generate the load instruction’s source address in advance. The load-centric design decreases the stall latency of load instructions and therefore improves the pipeline’s performance and energy efficiency. Experimental results show that equipped with a 4KB size prediction table, the load-centric design can improve the pipeline performance and energy efficiency by 8.6% and 7% respectively