• 中国计算机学会会刊
  • 中国科技核心期刊
  • 中文核心期刊

Computer Engineering & Science

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Impact of junction depth on SET pulse width
in 65nm bulk CMOS transistor

LIU Rong-rong,CHI Ya-qing,DOU Qiang   

  1. (College of Computer,National University of Defense Technology,Changsha 410073,China)
  • Received:2016-03-14 Revised:2016-12-07 Online:2017-12-25 Published:2017-12-25

Abstract:

We investigate the impact of N+-N,P+-P and PN junction depth on the single-event transient (SET) pulse width in nano technology through TCAD simulations. The variations of voltage or temperature are also considered. Simulation results indicate that N+-N junction plays the most important role in influencing the SET pulse width. Meanwhile, we also investigate the impact of voltage and temperature on junction depth. Simulation results indicate that the voltage can significantly affect N+-N and P+-P junction while the temperature can significantly affect PN junction.
 

Key words: N+-N junction, P+-P junction, PN junction, single-event transient (SET), PMOS, NMOS, pulse width