| [1] |
WAN Zirong, ZHANG Caizhen.
An improved error compensation image magnification algorithm based on FPGA implementation
[J]. Computer Engineering & Science, 2026, 48(3): 467-475.
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| [2] |
XIAO Jian, LI Zhibin, YANG Jin, CHENG Hongliang, HU Xin.
Research and implementation of a low-light image enhancement algorithm based on FPGA
[J]. Computer Engineering & Science, 2026, 48(1): 98-107.
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| [3] |
ZHENG Daowen1, ZHOU Yikai1, TANG Yibin2, 3, LIU Bosheng1, WU Jigang1.
ReHuff:A Huffman coding hardware architecture based on ReRAM
[J]. Computer Engineering & Science, 2025, 47(6): 988-997.
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| [4] |
YAN Shaohui, JIANG Jiawei, CUI Yu.
Image encryption and FPGA implementation based on 3D chaotic system
[J]. Computer Engineering & Science, 2025, 47(4): 686-694.
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| [5] |
SHEN Jinshang, ZHANG Qingshun, SONG Tierui.
Implementation of high-speed AES based on FPGA and improvement of MixColumn
[J]. Computer Engineering & Science, 2025, 47(4): 612-620.
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| [6] |
LI Zhenqi, WANG Qiang, QI Xingyun, LAI Mingche, ZHAO Yankang, LU Yihang, LI Yuan.
Design and FPGA implementation of lightweight convolutional neural network hardware acceleration
[J]. Computer Engineering & Science, 2025, 47(4): 582-591.
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| [7] |
XU Weikang, SUN Yan, ZHANG Jianmin.
A spiking neural network accelerator based on approximate computing
[J]. Computer Engineering & Science, 2025, 47(10): 1737-1744.
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| [8] |
RONG Peitao, ZENG Kun, LI Kai, ZHANG Tian, WANG Yongwen.
Research on state storage and strategic mapping techniques for FPGA-accelerated simulation
[J]. Computer Engineering & Science, 2025, 47(10): 1726-1736.
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| [9] |
WANG Peng, ZHANG Jia-cheng, FAN Yu-yang, .
A neural network pruning and quantization algorithm for hardware deployment
[J]. Computer Engineering & Science, 2024, 46(9): 1547-1553.
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| [10] |
CHEN Jie, LI Cheng, LIU Zhong.
Convolutional neural network inference and training vectorization method for multicore vector accelerators
[J]. Computer Engineering & Science, 2024, 46(4): 580-589.
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| [11] |
ZHAO Zhi-qiao, ZHOU Li, XUN Chang-qing, PAN Guo-teng, TIE Jun-bo, WANG Wei-zheng.
Efficient analysis of coherent hub interface protocol mixturing hardware and software
[J]. Computer Engineering & Science, 2024, 46(2): 224-231.
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| [12] |
MA Ke-fan, LI Bao-feng, ZHOU Yue-jin, WU Yuan-yuan, YU Yong-lan, DUO Rui-hua.
Design and implementation of a baseboard management controller on ZYNQ chip
[J]. Computer Engineering & Science, 2024, 46(2): 217-223.
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| [13] |
QIN Wen-qiang, WU Zhong-cheng, ZHANG Jun, LI Fang, .
Design of convolutional neural network acceleration system based on heterogeneous platform
[J]. Computer Engineering & Science, 2024, 46(1): 12-20.
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| [14] |
HU Qing-meng, , WANG Hong-bin, WANG Jun-zhong.
A Chinese event detection method based on nugget proposal network with part-of-speech attention mechanism
[J]. Computer Engineering & Science, 2023, 45(8): 1490-1497.
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| [15] |
YI Xiao, MA Sheng, XIAO Nong.
Running optimization of deep learning accelerators under different pruning strategies
[J]. Computer Engineering & Science, 2023, 45(7): 1141-1148.
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