[1] |
JIANG Jing-fei, HE Yuan-hong, XU Jin-wei, XU Shi-yao, QIAN Xi-fu.
NM-SpMM:A semi-structured sparse matrix multiplication algorithm for domestic heterogeneous vector processors
[J]. Computer Engineering & Science, 2024, 46(07): 1141-1150.
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[2] |
WANG Jie, FU Dan-yang, .
ROB compression method based on RISC-V superscalar processor
[J]. Computer Engineering & Science, 2024, 46(07): 1185-1192.
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[3] |
SHI Yang, CHEN Zhao-yun, SUN Hai-yan, WANG Yao-hua, WEN Mei, HU Xiao.
Design of independent software stack of FT-Matrix DSP
[J]. Computer Engineering & Science, 2024, 46(06): 968-976.
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[4] |
LIU Zhong, LI Cheng, TIAN Xi, LIU Sheng, DENG Rang-yu, QIAN Cheng-dong.
MVSim: A fast, scalable and accurate architecture simulator for VLIW multi-core vector processors
[J]. Computer Engineering & Science, 2024, 46(02): 191-199.
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[5] |
ZHENG Kang, LI Chen, CHEN Hai-yan, LIU Sheng, FANG Liang.
Design and optimization of scalar memory access unit in VLIW DSPs
[J]. Computer Engineering & Science, 2023, 45(11): 1929-1940.
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[6] |
ZHU Wen-long, JIANG Jia-zhi, HUANG Dan, XIAO Nong.
ParM: A heterogeneous programming model for domestic processors
[J]. Computer Engineering & Science, 2023, 45(09): 1521-1531.
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[7] |
SUN Cai-xia, SUI Bing-cai, DENG Quan, ZHENG Zhong, NI Xiao-qiang, WANG Yong-wen.
A hybrid ISA processor compatible with RISC-V at application level
[J]. Computer Engineering & Science, 2023, 45(08): 1347-1353.
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[8] |
ZHU Ying, TIAN Zeng, CHEN Ye, JIANG Yi-fei, LI Yan-zhe, LIU Xiao-qiang.
Design of an embedded processor with high reliability
[J]. Computer Engineering & Science, 2023, 45(03): 390-397.
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[9] |
CUI Xin-yue, JIANG Lin, YANG Kun, HUI Chao, HU Chuan-zhan, ZHAO Jing.
A dynamic self-reconfigurable implementation method of HEVC intra prediction algorithm
[J]. Computer Engineering & Science, 2022, 44(12): 2120-2127.
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[10] |
ZANG Zhao-hu, LI Chen, WANG Yao-hua, CHEN Xiao-wen, GUO Yang .
A hierarchical hardware barrier synchronization design for many-core processors
[J]. Computer Engineering & Science, 2022, 44(11): 1901-1908.
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[11] |
GUO Pan-pan, CHEN Meng-xue, LIANG Zu-da, MA Xiao-chang, XU Bang-jian.
Optimization of dot product algorithms on FT-M7002
[J]. Computer Engineering & Science, 2022, 44(11): 1909-1917.
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[12] |
LU Song, JIANG Ju-ping, REN Hui-feng.
Quick customization for RISC-V processor based on FPGA
[J]. Computer Engineering & Science, 2022, 44(10): 1747-1752.
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[13] |
CHEN Zi-yu, HE Jun, GUO Xiang-yu.
Implementation of cryptographic instructions for general purpose processors
[J]. Computer Engineering & Science, 2022, 44(07): 1162-1170.
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[14] |
LI Hui, JU Peng-jin, JI Yong-xing.
Error tracing and location technology in multi-processor cache coherence verification
[J]. Computer Engineering & Science, 2022, 44(07): 1171-1180.
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[15] |
GONG Rui, SHI Wei, LIU Wei, ZHANG Jian-feng, WANG Lei.
Design and implementation of CPU secure boot based on NAND Flash
[J]. Computer Engineering & Science, 2022, 44(06): 971-978.
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