Abstract: Hardware emulator is an important means to speed up the verification of Time-Sensitive Networking (TSN) chips. Since TSN chips are far less complex than SoCs (System on Chips), CPU-based hardware emulators can already meet the performance requirements of TSN chip verification. To meet the needs of the TSN chip design, a hardware emulator called OpenEmulator (abbreviated as OE) for the verification of TSN chips is designed and implemented. According to the characteristics of TSN system emulation, a time synchronization mechanism applied to OpenEmulator, called time interlock, is proposed, which realizes precise time synchronization between the physical domain running the real TSN application and the emulation domain running the hardware logic programed by the hardware description language (HDL). At present, OpenEmulator has been applied in the design process of OpenTSN chips. Based on a common PC, OpenEmulator can emulate the initialization of a 6-node TSN network and the subsequent first clock synchronization process in 20 minutes, greatly improving the efficiency of TSN chip emulation verification. Now, OpenEmulator has been open-sourced and integrated into the newly released version of the OpenTSN open source project (version 3.4).

Key words: time-sensitive networking (TSN), chip verification, co-emulation, time synchronization, time interlock